PQC-IMC: A Memristor-based In-Memory Computing Architecture for Accelerating Post-Quantum Cryptography Lattice-Based Operations

Abstract

The rapid rise of quantum computing threatens to undermine existing public-key cryptographic methods, driving an urgent push for Post-Quantum Cryptography (PQC) solutions. Lattice-based cryptographic protocols, including Kyber for key encapsulation and Dilithium for digital signatures, have emerged as top contenders due to their robust security. Yet, deploying these schemes in low-power IoT and edge platforms remains challenging, largely because polynomial multiplication—central to their operations—demands substantial computational resources. Standard von Neumann computer systems struggle with these tasks due to inefficiencies in shuttling data between memory and processor. This study presents PQC-IMC: a new in-memory computing (IMC) framework built on memristor (MR) crossbar arrays to accelerate the most intensive arithmetic steps in lattice-based PQC. We introduce a memristor-centric processing unit that executes Number Theoretic Transform (NTT) and point-wise multiplication directly where data is stored. Harnessing the parallelism and analog strengths of MR crossbars, PQC-IMC minimizes data transfer bottlenecks. Our comprehensive hardware blueprint features a coefficient mapping scheme for the crossbar and a digital circuit for managing operations and modular arithmetic. The system’s polynomial multiplication core was prototyped on a Xilinx Artix-7 FPGA using an MR emulator. Evaluation results show that PQC-IMC delivers a 4.1-fold speed increase and cuts energy use by 68% per polynomial multiplication compared to an optimized ARM Cortex-M4 software approach. Additionally, it achieves an 83% lower energy-delay product (EDP) than a leading ASIC accelerator. These outcomes highlight IMC’s potential for enabling secure, quantum-resistant cryptography in next-generation, energy-conscious edge devices.